1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus with a power-meshed structure.
2. Related Art
Accessing data in a semiconductor memory apparatus needs operating voltages such as an external power supply voltage, a ground voltage, an internal voltage, a reference voltage and a high voltage. The operating voltages are transferred to cell regions of the semiconductor memory apparatus through power lines.
FIG. 1 is a plan view illustrating a power line structure of a typical semiconductor memory apparatus. Referring to FIG. 1, in a semiconductor memory apparatus, as an integration density and a storage capacity increase geometrically, the number of signal lines S also increases. Because of this, the area the signal lines S are disposed occupies a majority part of a cell array region 10. Power lines P1 and P2 are disposed to extend horizontally and vertically in driving circuit regions 12, 15 and 18 which are defined on the peripheries of the cell array region 10. The power lines P1 and P2, which have the same levels, are connected to each other in a meshed structure through via contacts 20.
The power lines P1 and P2 are disposed in the relatively narrow driving circuit regions 12, 15 and 18. As the integration density of the semiconductor memory apparatus gradually increases, the number and the line width of the power lines P1 and P2 gradually decrease and it is difficult to secure the necessary resistance of the power lines P1 and P2.
If the resistance of the power lines P1 and P2 is not secured when a preset current to a certain current source is necessary, a power supply voltage (VDD) may fluctuate over time, which may result in malfunction of the semiconductor memory apparatus.